A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. One or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. In many hardware applications, such as, graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems which benefit substantially from a very fast bus transfer rate. In many computer system architectures of today, the majority of the above mentioned subsystems reside on the computer system's expansion bus, particularly, a PCI expansion bus (hereafter PCI bus).
PCI bus systems constitute an industry standardized, widely known, and widely used approach for transporting data within a computer system. Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, coupled to a host PCI bridge containing arbiter 106 (hereafter arbiter 106) through a CPU local bus 108 and memory bus 110, respectively. A PCI bus 112 is coupled to each of PCI agents 114, 116, 118, 120, 122, 124 respectively, and is additionally coupled to arbiter 106.
Referring still to Prior Art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, e.g., interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from arbiter 106. Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Arbiter 106 grants PCI bus ownership to one of the requesting PCI agents. Where there are simultaneous requests for PCI bus ownership, arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates a transaction (e.g., data transfer) with a "target device" or destination device (e.g., main memory 104). When the transaction is complete, PCI bus 112 is relinquished to arbiter 106, with arbiter 106 subsequently granting PCI bus 112 to a next requesting PCI agent.
Prior Art FIG. 2 shows a request grant architecture 200 of PCI bus architecture 100. PCI agents 114-124 are coupled to arbiter 106 via respective pairs of request lines REQ0#, REQ1#, REQ2#, REQ3#, REQ4#, and REQ5# (hereafter, request lines) and grant lines GNT0#, GNT1#, GNT2#, GNT3#, GNT4#, and GNT5# (hereafter, grant lines). The request signal lines and the grant signal lines comprise the arbitration control signal lines of PCI bus 112. However, unlike other PCI bus functional signal lines, each of PCI agents 114-124 are coupled to PCI bus 112 via its own particular request line and its own particular grant line, as shown in request grant architecture 200.
Referring still to Prior Art FIG. 2, PCI agents 114-124 request PCI bus ownership by asserting a request signal via their respective request lines. When several PCI agents request PCI bus ownership simultaneously, each requesting PCI agent asserts its respective request line. Arbiter 106 selects which of the requesting PCI agents should receive PCI bus ownership. Arbiter 106 then grants ownership by asserting the grant line corresponding to the selected PCI agent. While several of PCI agents 114-124 might have their request lines asserted, requesting PCI bus ownership from arbiter 106, at any given time, only one PCI agent will have its corresponding grant line asserted. Thus, at any given time, only one of PCI agents 114-124 will own PCI bus 112.
A first problem with the prior art request grant architecture 200 is the nature of the arbitration process. In the PCI specification (which defines the basic rules governing the operation of the PCI bus), typically, only one PCI agent can own PCI bus 112 at a time. The owning PCI agent maintains exclusive use of PCI bus 112 while executing its transaction. Other of PCI agents 114-124 requesting PCI bus ownership await a grant of PCI bus 112 from arbiter 106. In order to insure efficient allocation of PCI bus bandwidth, arbiter 106 should allocate ownership of PCI bus 112 fairly among PCI agents 114-124.
In addition, arbiter 106 should account for relative priority among PCI agents 114-124. Some PCI agents may request PCI bus ownership often and require ownership promptly due to the nature of their particular function, e.g., a local area network PCI agent, which must input and output large blocks of data promptly in order to function correctly. As such, a local area network PCI agent cannot tolerate large amounts of latency when it requests bus ownership. In comparison, an audio PCI agent typically does not constantly input and output of large contiguous blocks of data, and thus can tolerate some degree of latency.
The PCI specification does not define the method used by arbiter 106 to decide among competing PCI agents 114-124 when two or more request ownership of the PCI bus 112 at the same time. An algorithm used to decide which requesting PCI agent will be granted PCI bus ownership is often system specific. A system designer is free to determine the logic characteristics of the arbitration algorithm. Generally, prior art algorithms are simply designed to ensure high priority peripherals will not dominate the PCI bus to the exclusion of lower priority peripherals. What is required in an algorithm which can intelligently allocate PCI bus bandwidth among PCI agents of differing priority without adding unnecessary latency to the arbitration process. Such an algorithm should adequately account for priority differences among requesting PCI agents at all times possible.
A second problem is the accommodation of additional PCI agents within PCI bus architecture 100. The functions of a PCI bus architecture are implemented by a PCI chipset. A PCI chipset is a set of integrated circuits which implement the functions and parameters of the PCI bus specification. The PCI chipset defines and implements the specifications and characteristics of the PCI bus. There are a limited number of PCI agents which may be accommodated by a PCI chip set. Thus, there are a limited number of slots in which to incorporate PCI agents. If more PCI agents are desired, a hierarchical bridge to a subordinate PCI bus, which will accommodate its own set of PCI agents, is typically incorporated. The disadvantages of this solution include the added expense of the chipset implementing the PCI-to-PCI bridge function, and the bus transfer latencies added to the PCI agents on the subordinate bus.
Thus, a need exists for a system which can efficiently allocate PCI bus bandwidth among PCI agents of differing priority without adding unnecessary latency to the arbitration process. A further need exists for a system which efficiently interfaces additional PCI agents without incurring the performance and expense penalties of adding a PCI-to-PCI bridge.